Recent trends in semiconductor device applications, especially mobile device applications, include a push towards higher performance levels while maintaining low power consumption, cost, and area. In order to achieve these goals, vendors and semiconductor device manufacturers are exploring solutions for increasing memory capacity of the devices, reducing package size, improving testability, and integrating passive components efficiently in device packages. The state of the art related to device packages will be discussed briefly with a few examples to illustrate benefits as well as weaknesses in known solutions.
Firstly, with regard to FIG. 1, a multiple package solution will be discussed. FIG. 1 illustrates a conventional package-on-package (PoP) 100. PoP 100 includes at least the two illustrated packages 102 and 104 attached to each other. Package 104 includes logic die 106, and package 102 includes one or more memory dies, such as memory dies 108a and 108b. Accordingly, logic die 106 and memory dies 108a-108b may be packaged separately and the packages attached to each other. Wire bonds 114 and/or through mold vias (TMVs) 112 are also typically used for electrically connecting logic die 106 and memory dies 108a-b. 
In the illustrated configuration, PoP 100 has several attractive features. In general it allows for close proximity and control of relative placement of logic die 106 and memory dies 108a-b. Testability of individual dies is also improved because the logic and memory dies can be separately tested, and only dies which pass the tests (also known as “known good dies”) are packaged. This keeps costs low and allows the ability to customize memory needs for particular processors. Moreover, there is improved flexibility in the sourcing of memory dies 108a-b. For example, memory dies 108a-b may comprise dynamic random access memory (DRAM). DRAM dies of different sizes and/or from different vendors/manufacturers can be easily integrated into package 102, to suit particular needs of a processor integrated on logic die 106, for example.
However, PoP 100 suffers from several drawbacks. Typically, PoP structures such as PoP 100 include vertical stacking of the packages comprising logic and memory dies. This leads to an undesirable increase in the total height of PoP 100. Further, wire bonds 114 create long paths between logic die 106 and memory dies 108a-b. The pitch of TMVs 112 tends to be high because of the thickness of the packages/molds that need to be traversed to interconnect logic die 106 and memory dies 108a-b. Moreover, passives, such as the illustrated capacitor 110 are not integrated efficiently in typical PoP structures, and this leads to an increased footprint (horizontal area). Narrow input/output (I/O) interfaces, or rather, a lack of support for wide I/O interfaces, are seen as yet another limitation of PoP 100.
Rather than package the logic and memory dies separately as in PoP 100, single package solutions are also known in the art, and will be described with regard to FIGS. 2-3. In FIG. 2, a so called “3D package” structure 200 is illustrated. 3D package 200 comprises a unified package 202 that encapsulates logic die 204, as well as, DRAM die 206. Logic die 204 and DRAM die 206 are vertically integrated. One improvement of 3D package 200 over PoP 100 is that the lengths of interconnections 208, for example, between logic die 204 and DRAM die 206 are significantly reduced, as these do not have to traverse package molds. Additionally, 3D package 200 can support very wide I/O interfaces, which enables high bandwidth memory access.
However, 3D package 200 also suffers from several drawbacks. The unified package structure leads to loss of flexibility in sourcing the DRAM die, at least prior to I/O standardization. Once again, package height, although lower than PoP 100, is still high in 3D package 200 due to the vertical integration of logic die 200 and DRAM die 206. Thermal management is a problem, because it is difficult to contain the heat propagation from logic die 204 to DRAM die 206. Moreover, redistribution layer (RDL) 210 is typically needed to enable integration of DRAM die 206 with logic die 204. RDL 210 tends to be expensive and leads to increase in cost of 3D package 200.
FIG. 3 illustrates another single package solution, referred to herein, as a “2.5D package.” More specifically, FIG. 3 illustrates 2.5D package with interposer 300, which includes package 302. Package 302 also encapsulates logic die 304 and DRAM die 302 in a single package or mold. Rather than vertically stacking logic die 204 and the DRAM die 206 as in 3D package 200 above, package 302 involves a side-by-side placement of logic die 304 and DRAM die 306. The logic and memory dies are connected by an interposer structure through which electrical connections can be formed. As shown, package 302 includes interposer 308 formed on substrate 312. Interposer 308 is typically formed from silicon, and includes through silicon vias (TSVs) 310 for connecting the two dies. Such an interposer configuration is seen to keep the length of interconnections low, while also supporting wide I/O interfaces for high bandwidth memory access. Interposer 308 also provides additional structural support for logic die 304 and DRAM die 306. Significantly, the height of package 302 is low due to the horizontal side-by-side placement of logic die 304 and DRAM die 306, rather than vertically stacking them as in 3D package 200 and PoP 100 above. This also improves thermal management because heat does not directly propagate from logic die 304 to DRAM die 306.
However, 2.5D package with interposer 300 also suffers from several deficiencies. The cost of the typical interposer is high, and TSV technology is expensive. Moreover, this structure reduces package height at the cost of a large package footprint.
With reference to FIG. 4, package 400 according to Applicant's co-pending and commonly owned U.S. patent application Ser. No. 13/766,218, entitled “semiconductor device having stacked memory elements and method of stacking memory elements on a semiconductor device,” is illustrated. Package 400 overcomes several of the drawbacks of packages 100-300 of FIGS. 1-3 discussed above, and provides a stacking arrangement with improved mechanical stability and thermal management, while reducing the footprint of the package. In relevant aspects, FIG. 4 illustrates package 400 comprising logic die 402 mounted on package substrate 404 which includes redistribution layer (RDL) 406. A first memory device, DRAM 410 is coupled to RDL 406 by microbumps 416 at a first location on the redistribution layer 406 so that logic die 402 can communicate with the first memory device 410. An interposer formed of Silicon, interposer 418 is mounted on RDL 406, adjacent to DRAM 410. Microbumps 424 on interposer 418 provide an electrical connection between interposer 418 and a second location on RDL 406. Interposer 418 also includes through-vias (not illustrated), such as, TSVs, to connect locations on top surface 422 of interposer 418 to microbumps 424 and provide an electrical pathway through interposer 418. This configuration of logic die 402, interposer 418, and DRAM 410 provides mechanical stability to the stacking arrangement, while reducing the footprint, as compared to 2.5D package with interposer 300, for example.
Moreover, a second memory device, DRAM 426 can be mounted on and coupled to interposer 418 with microbumps 428, to provide an electrical connection between DRAM 426 and interposer 418. Beneficially, this arrangement also reduces the length of electrical connections between DRAM 426 and logic die 402, as compared to coplanar mounting arrangements or PoP 100, for example. Spacer 430, which may be thermally conductive, may be mounted on a remaining portion of top surface 412 of DRAM 410. Spacer 430 may be formed of silicon or other material having comparable thermal and mechanical properties and may enhance mechanical integrity by equalizing mechanical stresses in a molded package including the first and second memory devices and also enhance heat transfer. Thus, package 400 may also provide an improved solution for thermal management as compared to 3D package 200, for example.
However, in some aspects, silicon interposer 418 also involves the use of expensive TSVs. The TSV technology can impose restrictions on pitch, and may, for example, limit thickness of interposer 418 to 100 um. In order to retain mechanical stability and prevent excessive overhang of the memory devices (e.g. DRAM 410) and interposer 418 over the so called “tier 1” die, which includes logic die 402 and RDL 406, restrictions are placed on the size of interposer 418. In other words, the size of interposer 418 is dependent on, or limited by, the size of logic die 402, which can, in turn, impose restrictions on TSV placement and design of interconnections through interposer 418. Moreover, package 400 is configured for a single package solution, and does not offer the flexible design choices which are possible in a PoP solution. Testing may be performed at the final package level. Wafer level testing to determine known good dies is possible, but fine pitch TSV testing cannot be performed.
Accordingly, there is a need for semiconductor device package structures which overcome the aforementioned drawbacks, while also providing desirable features, such as, low package height, small footprint, flexibility in DRAM sourcing, minimization or elimination of an RDL layer, low cost interposers, etc.